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supertex inc. supertex inc. www.supertex.com doc.# dsfp-hv633 c031414 hv633 features ? hvcmos ? technology ? 5.0v cmos inputs ? capable of 128 levels of gray shading ? modulation voltage up to +80v ? 24mhz data throughput rate ? 32 outputs per device (can be cascaded) ? pin-programmable shift direction (dir) ? d/a conversion cycle time is 20s ? diodes in output structure allow usage in energy recovery systems ? available in 3-sided 64-lead gull wing package applications ? electroluminescent displays ? polycholesteric displays functional block diagram 32-channel, 128-level amplitude gray-shade display column driver general descriptionthe hv633 is a 32-channel driver ic for gray shade display use. it is designed to produce varying output voltages between 3.0 - 80v. this amplitude modulation at the output is facilitated by an external ramp voltage v r . see theory of operation for detailed explanation. this device consists of dual 16-bit shift registers, 32 data latches and comparators, and control logic to preform 128 levels of gray shading. there are 7 bits of data inputs. data is shifted through the shift registers at both edges of the clock, resulting in a data transfer rate of twice that of the shift clock frequency. when the dir pin is high, csi/cso is the input/ output for the chip select pulse. when dir is low, csi/cso is the output/input for the chip select pulse. when the dir pin is high, it allows the hv633 to shift data in the counter-clockwise direction when viewed from the top of the package. when the dir pin is low, data is shifted in the clockwise direction. the output circuitry allows the energy which is stored in the output capacitance to be returned to v pp through the body diode of the output transistor. 32 hv out 1 hv out 32 vctl rctl v r v pp v dd csi sc lc cc cso dir d1 - d7 ~ ~ high voltage s ource follower output buffer i bias control low voltage s hift register latches comparator c ounter 7 downloaded from: http:///
2 supertex inc. www.supertex.com doc.# dsfp-hv633 c031414 hv633 absolute maximum ratings parameter value supply voltage, v dd -0.5v to +7.5v supply voltage, v pp -0.5v to +90v logic input levels -0.5v to v dd +0.5v ground current 1 1.5a operating temperature range 0c to +125c storage temperature range -65c to +150c continuous total power dissipation 2 2.0w absolute maximum ratings are those values beyond which damage to the device may occur. functional operation under these conditions is not implied. continuous operation of the device at the absolute rating level may affect device reliability. all voltages are referenced to device ground. notes: 1. duty cycle is limited by the total power dissipated in the package. 2. for operation above 25c ambient derate linearly to 125c at 20mw/c. recommended operating conditions sym parameter min typ max units v dd low-voltage digital supply voltage 4.5 5.0 5.5 v low-voltage analog supply voltage v ih high-level input voltage (analog & digital) v dd -1 - v dd v v il low-level input voltage (analog & digital) 0 - 1.0 v v bias i pp control circuit bias voltage -2.0 0 - v v ctl i pp control circuit control voltage - 0 2.0 v v pp high voltage supply -0.3 - 80 v v r ramp voltage 0 - v pp -2 v f sc shift clock operating frequency (at v dd = 5.5v) - - 12 mhz product marking l = lot number yy = year sealed ww = week sealed c = country of origin a = assembler id = green packaging top marking hv633pg llllllllll yyww cccccccc aaa pin coniguration 1 64 64-lead pqfp 64-lead pqfp (top view) package may or may not include the following marks: si or ordering information part number package option packing HV633PG-G 64-lead pqfp 66/tray typical thermal resistance package ja 64-lead pqfp 41 o c/w -g denotes a lead (pb)-free / rohs compliant package downloaded from: http:///
3 supertex inc. www.supertex.com doc.# dsfp-hv633 c031414 hv633 sym parameter min typ max units conditions i dd v dd supply current - 12 20 ma f sc = 12mhz, f cc = 12mhz i ddq quiescent v dd supply current - - 200 a all v in = 0v, v dd = 5.5v i ih high-level input current - 1.0 50 a v ih = v dd i il low-level input current - -1.0 -50 a v il = 0v c in 2 input capacitance (d1 ~ d7, lc, sc, cc) - - 15 pf v in = 0v, f = 1.0mhz i oh high-level output current -2.0 - - ma v dd = 4.5v, v oh = 0.9v dd i ol low-level output current 2.0 - - ma v dd = 4.5v, v ol = 0.1v dd notes: 1. all typical values are at v dd = 5.0v. 2. guaranteed by design. low voltage dc characteristics (analog) i dd v dd supply current - - 500 a f sc = 12mhz, f cc = 12mhz i ddq quiescent v dd supply current - - 200 a all v in = 0v, v dd = 5.5v high voltage bias circuit for output variation control i pp v pp supply current for bias circuit - 2.0 - ma depending on external bias circuit, see table 1. high voltage dc characteristics i aoh high-voltage analog output source current see performance curves ma v pp = 80v. see test circuit i aol high-voltage analog output sink current see performance curves ma v pp = 80v, v dd = 4.5v, v ao = 2.0v v o maximum delta voltage between high voltage outputs of the same level - - 0.2 v at all gray levels ac characteristics (v dd = 5.5v, t a = 25c) logic timing f sc shift clock operating frequency - - 12 mhz --- f din data-in frequency - - 24 mhz --- t ss csi/cso pulse to shift clock setup time - 40 - ns --- t hs csi/cso pulse to shift clock hold time - 0 - ns --- t wa csi pulse width - 49 - ns --- t ds data to shift clock setup time - 20 - ns --- t dh data to shift clock hold time - 0 - ns --- t wd data-in pulse width - 24 - ns --- t wlc load count pulse width - 98 - ns --- t dlcr load count to ramp delay 1.0 - - s --- t drcc 3 ramp to count clock delay 0.47 - - s --- t dsl shift clock to load count delay time - 98 - ns --- electrical characteristics (over recommended operating conditions at t a = 25c unless otherwise noted) low voltage dc characteristics (digital) 1 downloaded from: http:///
4 supertex inc. www.supertex.com doc.# dsfp-hv633 c031414 hv633 sym parameter min typ max units conditions t csc shift clock cycle time 98 - - ns --- t wsc shift clock pulse width 49 - - ns --- t ccc count clock cycle time 98 - - ns --- t wcc count clock pulse width 49 - - ns --- v r timing t cr cycle time of ramp signal 15 - - s --- t rr ramp rise time 10.6 - - s --- t hr 4 ramp hold time 2.0 - 15 s --- t fr ramp fall time 3.0 - - s c load = 1nf notes: 3. count clock starts counting after 0.47s min. this is equivalent to a time duration for a linear ramp v r to ramp from 0 to 3.0v, assuming the minimum value of t rr , ramp size time of 12s for v r = 80v. 4. the maximum ramp hold time may be longer than 15 s, but the output voltage hv out will droop due to leakage . logic timing (cont.) option 1 option 2 v bias (v) v ctl (v) r ctl (k) i pp (ma) v bias (v) v ctl (v) r ctl (k) i pp (ma) 0 0.1 56 2.0 -1.0 0 56 4.0 0 1.0 56 7.0 -2.0 0 56 5.5 table 1: schemes to control i pp bias current, typical i pp v ctl r ctl v bias - + hv633 vctlrctl - + function dir data in (d1 - d7) csi cso sc lc cc v r hv out shift data from hv out 1 to hv out 32 h data output l l l data hv out 1 ... hv out 32 shift data from hv out 32 to hv out 1 l data output l l l data hv out 32 ... hv out 1 load shift register x x pre-deined by 1 or 2 l l l - load counter x x l l l - counting/voltage conversion x x l l initiates v r - function table notes: l = low logic level h = high logic level = low to high transition = transition of both edges x = dont care downloaded from: http:///
5 supertex inc. www.supertex.com doc.# dsfp-hv633 c031414 hv633 latches and comparators latches and comparators latches and comparators latches and comparators load count cc vr gnd vpp hv out 1 output stage hv out 2 hv out 31 vctlrctl counter reset counter hv out 32 rs f/f rs f/f rs f/f rs f/f 7 7 7 7 7 7 7 7 7 l/e l/e l/e l/e sc sc dir s ee o utput s tage detail 1 2 31 32 dual 16-bit shift registers data latches data latches data in buffers output stage output stage load count buffer count clock buffer cc lc clear pulse generator d1 d7 sc shift clock buffer cso i/o buffers csi i/o buffers data latches data latches output stage functional block diagramnote: sc = shift clock, lc = load count, cc = count clock, csi = chip select input, cso = chip select output*data rate = 2x the sc frequency input and output equivalent circuits vdd da ta in lv gnd logic inputs da ta out logic data output vdd lv gnd output stage detail vctl rctl vr v pp c h q 1 q 2 hv out internal logic & bias circuit downloaded from: http:///
6 supertex inc. www.supertex.com doc.# dsfp-hv633 c031414 hv633 test circuit high-voltage analog output source current (i aoh ). for gray shade #1 (000 0000). logic 70v hv633 0v output stage vr hvgnd lvgnd vpp = 80v + C hvout 1.0k v tst 10k + - 1 32 1 32 1 32 32 1 32 1 32 1 vr, vpp lvgnd, hvgnd, sc, lc, cc, cso vr, vpp lvgnd, hvgnd, sc, lc, cc, csi d1 ~ d7 dir = low dir = high d1 ~ d7 display panel (example) typical panel connections 1. set hv out = low 2. apply v pp = 80v 3. apply a step voltage of 70v at v r (slew rate = 4.1v/s) 4. measure voltage across the 1.0k resistor 5. output source current can be calculated by using v tst /1.0k downloaded from: http:///
7 supertex inc. www.supertex.com doc.# dsfp-hv633 c031414 hv633 timing diagrams chip select input (csi) load first device load second device load last device 12 345 128 t rr t fr t dlcr vr chip select output (cso) shift clock (sc) load count* (lc) count clock (cc) hv out data from data bus (see detailed ti m ing) t cr t hr *hv out will clear to zero with load count. 12 345 12 da ta in (d1 - d7) t t ss t hs da ta set 1 da ta set 2 da ta set 3 da ta set 31 da ta set 32 t ds t dh t wd t wlc t ds l da ta set 1 da ta set 31 loading last device next loading cycle chip select input (csi) data (d1-d7) shift clock (sc) load count (lc) count clock (cc) count clock 1 count clock 128 0v 3v t drcc t dlcr t csc sc2 sc 16 sc 1 sc 16 t wcc t ccc sc1 (b) detailed device ti ming (a) basic system ti ming vr t wsc downloaded from: http:///
8 supertex inc. www.supertex.com doc.# dsfp-hv633 c031414 hv633 gray shade decoding scheme gray scale voltage 0 vr hv out hv out hv out hv out hv out 1 2 127 gray scale voltage clock cycle (000 0000) ( 111 1111 ) shade number d7 d6 d5 d4 d3 d2 d1 128 1 1 1 1 1 1 1 127 1 1 1 1 1 1 0 126 1 1 1 1 1 0 1 125 1 1 1 1 1 0 0 124 1 1 1 1 0 1 1 123 1 1 1 1 0 1 0 122 1 1 1 1 0 0 1 121 1 1 1 1 0 0 0 ?? ? ?? ? ?? ? ?? ? ?? ? ?? ? ?? ? ?? ? 7 0 0 0 0 1 1 0 6 0 0 0 0 1 0 1 5 0 0 0 0 1 0 0 4 0 0 0 0 0 1 1 3 0 0 0 0 0 1 0 2 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 typical performance curves sink output characteristics source output characteristics v gs volts v gs volts i o (milliamperes) i o (milliamperes) 02 14 35 67 80 2 14 35 67 8 1512 96 3 0 1512 96 3 1 downloaded from: http:///
9 supertex inc. www.supertex.com doc.# dsfp-hv633 c031414 hv633 theory of operationthe hv633 has two primary functions: 1) loading data from the data bus and, 2) gray-shade conversion(converting latched data to out - put voltages). since the device was developed initially for lat panel dis - plays, the operation will be described in terms that pertain to that technology. as shown by the typical panel connec - tions, several hv633 packages are mounted at the top and bottom of a display panel. data exists on a 7-bit bus (adja - cent pc board traces) at top and bottom. the d1 through d7 inputs of each chip take data from the bus when either a csi or cso pulse is present at the chip. these pulses there - fore act as a combination chip select and location strobe. because of the way the chip hv out pins are se - quenced, data on the bus at the bottom of the display panel will be entered into the left-most chip as hv out 1, hv out 2, etc. up to hv out 32. the csi pulse will accomplish this with dir = high. loading data from data bus here is the full data-entry sequence: 1) the micro controller puts data on the bus (7 bits) 2) to enter the data into the 32 sets of 7 latches on the irst chip, the shift clock rises. this positive transition is combined with the csi pulse and is generated only once to strobe the data into the irst set of latches. (these latches eventually send data to the hv out 1). the data on the bus then changes, the shift clock falls, and this negative transition is combined with the csi pulse, which is now propagated internally, to strobe the new data into the next set of 7 latches (which will end up as hv out 2). this internal csi pulse therefore runs at twice the shift clock rate.3) when the last set of 7 latches in the irst chip has been loaded (hv out 32), the csi pulse leaves chip 1 and enters chip 2. the exit pin is called cso and the chip 2 entry pin is csi. for chips at the top of the panel things are reversed: dir is low, entry pins are cso and exit pins are csi, be - cause the data-into-latches sequence is in descending or - der, hv out 32 down to hv out 1. 4) the buses may of course be separate, and data can be strobed in on an interleaved basis, etc., but those complica - tions will be left to systems designers. when data has been loaded into all 32 outputs of all chips (top and bottom of the display panel), the load count pin is pulsed. on its rising transition, all output levels are reset to zero and all the data in the input latches is transferred to a like number of comparator latches, (thus leaving the data latches ready to receive new data during the following op - erations). after the transfer, the load count pin is brought low. this transition begins the events that convert the binary data into a gray-shade level. gray-shade conversion 1) the count clock is started. an external signal is ap - plied to the count clock pin, causing the counter on each chip to increment from binary 000 0000 to 111 1111 (0 to 127). 2) at the same time, the v r voltage is applied to all chips, via charging transistors, causing the hold capacitor (ch) on each output to experience a rise in voltage. 3) the logic control compares the count in the comparator latch to the count clock. the gate voltage of q1 and the out - put voltage hv out will ramp up at the same rate as vr. 4) once v r has reached the maximum voltage, then all the pixels will be at the inal value. (see gray scale voltage.) output voltage variation the output voltage of the hv633 is determined by the logic and the ramp voltage v r . it is possible that the output volt - age may be coupled to an unacceptable level due to its adjacent outputs through the panel. in order to solve this problem, internal logic (refer to output stage detail) is in - tegrated in the ic to minimize the effect. two external pins vctl and rctl allow the feasibility to control the current lowing through q2. the vctl pin is connected to a voltage source and the rctl pin is connected to ground through a resistor (2.0v and 56k are used for a particular panel). the internal bias circuit will drive the resistor to a voltage level that is equal to the vctl voltage at steady state through an operational ampliier. the current lowing through q1 and q2 will be limited to vctl/rctl. this combination of vctl and rctl will reduce the output voltage variation to less than 0.2v of delta voltage for each gray shade, independent of its adjacent output voltages. downloaded from: http:///
10 supertex inc. www.supertex.com doc.# dsfp-hv633 c031414 hv633 pin descriptions pin # function description 1 hv out 1 high-voltage outputs 2 hv out 2 3 hv out 3 4 hv out 4 5 hv out 5 6 hv out 6 7 hv out 7 8 hv out 8 9 hv out 9 10 hv out 10 11 hv out 11 12 hv out 12 13 hv out 13 14 hv out 14 15 hv out 15 16 hv out 16 17 hvgnd this is ground for the high-voltage (output) section. hvgnd and lvgnd should be connected together externally. 18 vr high voltage ramp input for charging the output stage hold capacitors (ch). this input can be linear or non-linear as desired. 19 vpp this input biases the output source followers. 20 nc no connect. 21 vdd (analog)* low-voltage analog supply voltage. 22 csi input pin for the chip select pulse (when dir is high). output pin for the chip select pulse (when dir is low). 23 nc no connect. 24 vctl voltage supply pin to prevent output voltage from being affected by its adjacent outputs (v ctl = 2.0v for a particular panel). the combination of v ctl and r ctl will reduce the output voltage variation to less than 0.2v of delta voltage between high voltage outputs of the same level at all gray levels. 25 rctl current sense resistor to ground to prevent output voltage from being affected by its adjacent outputs (r ctl = 56k for a particular panel). see vctl function above. 26 sc (shift clock) triggers data on both rising and falling edges. this implies that the data rate is always twice the clock rate (data rate = 20mhz if clock rate = 10mhz). 27 lvgnd this is ground for the logic section. hvgnd and lvgnd should be connected together externally. 28 dir when this pin is connected to vdd, input data is shifted in ascending order, i.e., corresponding to hv out 1 to hv out 32. when connected to lvgnd, input data is shifted in descending order, i.e., corresponding to hv out 32 to hv out 1. 29 vdd (digital)* low-voltage digital supply voltage. * analog vdd and digital vdd may be connected seperately for better noise immunity. downloaded from: http:///
11 supertex inc. www.supertex.com doc.# dsfp-hv633 c031414 hv633 pin # function description 30 d7 inputs for binary-format parallel data. 31 d6 32 d5 33 d4 34 d3 35 d2 36 d1 37 nc no connect. 38 lvgnd this is ground for the logic section. hvgnd and lvgnd should be connected together externally. 39 nc no connect. 40 lc (load count) input for a pulse whose rising edge causes data from the input latches to enter the comparator latches, and whose falling edge initiates the conversion of this binary data to an output level (d-to-a). also, the hv out will clear to zero after the load count is initiated. 41 nc no connect. 42 cc (count clock) input to the count clock generator whose increments are compared to the data in the comparator latches. 43 cso input pin for the chip select pulse (when dir is low). output pin for the chip select pulse (when dir is high). 44 nc no connect. 45 vpp this input biases the output source followers. 46 nc no connect. 47 vr high-voltage ramp input for charging the output stage hold capacitors (ch).this input can be linear or non-linear as desired. 48 hvgnd this is ground for the high-voltage (output) section. hvgnd and lvgnd should be connected together externally. 49 hv out 17 high-voltage outputs 50 hv out 18 51 hv out 19 52 hv out 20 53 hv out 21 54 hv out 22 55 hv out 23 56 hv out 24 57 hv out 25 58 hv out 26 59 hv out 27 60 hv out 28 61 hv out 29 62 hv out 30 63 hv out 31 64 hv out 32 pin descriptions (cont.) downloaded from: http:///
supertex inc. does not recommend the use of its products in life support applications, and will not knowingly sell them for use in such applications unless it receives an adequate product liability indemnification insurance agreement. supertex inc . does not assume responsibility for use of devices described, and limits its liabilit y to the replacement of the devices determined defective due to workmanship. no responsibility is assumed for possible omissions and inaccuracies. circuitry and specifications are subject to change without notice. for the latest product specifications refer to the supertex inc . (website: http//www .supertex.com) ?2014 supertex inc. all rights reserved. unauthorized use or reproduction is prohibited. supertex inc. 1235 bordeaux drive, sunnyvale, ca 94089 t el: 408-222-8888 www.supertex.co m 12 hv633 (the package drawing(s) in this data sheet may not relect the most current speciications. for the latest package outline information go to http://www.supertex.com/packaging.html .) doc.# dsfp-hv633 c031414 64-lead pqfp (3-sided) package outline (pg) 20.00x14.00mm body, 3.40mm height (max), 0.80mm pitch, 3.90mm footprint symbol a a1 a2 b d d1 e e1 e l l1 l2 l3 1 dimen- sion (mm) min 2.80 0.25 2.55 0.30 22.25 19.80 17.65 13.80 0.80 bsc 0.73 1.95 ref 0.25 bsc 0.55 ref 0 o 5 o nom - - 2.80 - 22.50 20.00 17.90 14.00 0.88 3.5 o - max 3.40 0.50 3.05 0.45 22.75 20.20 18.15 14.20 1.03 7 o 16 o drawings not to scale.supertex doc. #: dspd-64pqfppg, version nr090608. note: 1. a pin 1 identiier must be located in the index area indicated. the pin 1 identiier can be: a molded mark/identiier; an embedded metal marker; or a printed indicator. 2. the leads on this side are trimmed. 1 64 vi ew b side view top vi ew note 1 (index area d1/4 x e1/4) l3 note 2 seating plane gauge plane l l1 l2 view b seating plane a2 a a1 d e e1 d1 b e 1 downloaded from: http:///

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